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Features
* Integrates a 64-slot Digital Signal Processor (DSP), 16-bit Processor, 24K x 16 On-chip
Flash Memory, 2K x 16 RAM, 64 Individually Programmable I/O Pins
* Alternate Group Selectable I/O Pins Allow External Memory Expansion, Host Parallel
I/O, Serial MIDI_IN/MIDI_OUT, Additional Digital Audio-in/out
* Up to 64 Voices Polyphony, 24 dB Resonant Filter Per Voice, User Programmable
Synthesis/Processing Algorithms Three Timers, One Timer Being Available for Orchestrations Tempo Control Ideal for Battery Operation 3V to 4.5V Power Supply Power-down Mode Parameters Can Be Saved Into Built-in Flash Memory on a Single Word Write Basis. Compatible with ATSAM97xx Series Design Tools and Debugger Quick Time to Market Proven Reliable Synthesis Drivers In-circuit Emulation with Code View Debugger for Easy Prototype Development Built-in Flash Programming Algorithm Low frequency Input Clock at 256xFs Minimizes RFI, Built-in PLL Raises Frequency Internally * PQFP100 Easy Mount Standard Package (Pitch 0.65 mm) * Atmel Standard Flash Technology
* * * * * * * * * * *
Sound Synthesis ATSAM9743 Single-chip Music System
Description
The ATSAM9743 integrates into a single chip an ATSAM97xx core (64-slot DSP + 16bit processor), a 24K x 16 Flash memory, a 2K x 16 RAM, and up to 64 individually programmable I/O pins. With the addition of a single external digital-to-analog converter or a codec, the ATSAM9743 can be used in a variety of musical and sound processing applications, like low-cost keyboards, equalizers and effect processors. I/O pins can be configured for external memory expansion, allowing more sophisticated products with up to 4M bytes RAM or ROM. Figure 1. Typical Application of the ATSAM9743
Keyboard Switches LEDS LCD Display MIDI_IN/MIDI_OUT
ATSAM9743
DAC
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Principal Elements
Key Circuitry in a Single Chip The ATSAM9743 provides a new generation of integrated solutions for electronic musical instruments and sound processors. The ATSAM9743 places all key circuitry onto a single silicon chip: sound synthesizer/processor, 16-bit control processor, 24K x 16 Flash memory, 2K x 16 RAM, and up to 64 individually programmable I/O pins allowing direct interface with keyboard, switches, LCD display, etc. The synthesis/sound processing core of the ATSAM9743 is taken from the ATSAM97xx series, whose quality has already been demonstrated through dozens of different musical products such as electric pianos, home keyboards, professional keyboards, classical organs, sound expanders and effect devices. The maximum polyphony is 64 voices without effects. A typical application will be 38-voice polyphony with reverb, chorus, 4-band equalizer and surround. Configuration options allow the ATSAM9743 to cover a wide range of products, from the lowest cost keyboard to the high range multi-effect processor. Thanks to flexible external memory expansion, up to 4M bytes additional external memory can be used for firmware, orchestrations, PCM data or delay lines. The external memory can be ROM, RAM or Flash. The internal Flash memory can be programmed on-board from the ATSAM9743 itself by a Flash programming algorithm, which resides in internal ROM on chip. The ATSAM9743 operates from a single 8 MHz crystal. A built-in PLL multiplies by 4 the crystal frequency for internal processing. This minimizes radio frequency interference (RFI), making it easier to comply with FCC, CSA and CE standards. The ATSAM9743 is very suitable for battery-operated products: * * * Quick Time to Market A power-down feature is included which can be controlled externally (PDWN/ pin). Built-in Flash memory words can be individually programmed by the firmware itself. Operational voltage is from 3V to 5.5V (I/O).
ATSAM97xx Series Processing Core
External Memory Expansion
Standard Compliance Made Easier
Battery Powered Usage
The ATSAM9743 has been designed with final instrument quick time-to-market in mind. The ATSAM9743 product development program includes key features to minimize product development efforts: * * * * * Specialized debug interface, providing on-target software development with a source code CodeView debugger. Standard sound generation/processing firmware. Windows(R) tools for sounds, soundbanks and orchestration developments. Standard soundbanks. Comprehensive technical support available directly from Atmel.
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Internal Architecture
The highly-integrated architecture of the ATSAM9743 combines a specialized high-performance RISC-based digital signal processor (DSP) and a general-purpose 16-bit CISC-based control processor (P16). An on-chip memory management unit (MMU) allows the DSP and the control processor to share an internal 24K x 16 Flash memory, 2K x 16 RAM, as well as optional external ROM and/or RAM memory devices configured through the Ports & Flash control registers. An intelligent peripheral I/O interface function handles other I/O interfaces, such as the on-chip MIDI UART and three timers, with minimum intervention from the control processor. Four 16-bit I/O ports can have their bits individually configured as inputs or outputs, they can also be assigned alternate functions such as external memory access (address, data and control signals), 8-bit parallel MIDI port, serial MIDI_IN/MIDI_OUT, and additional digital audioin/out. See Table 2 on page 5 and Table 3 on page 6 for details. Figure 2. Diagram of the Internal Architecture of the ATSAM9743
CLBD WSBD DABD0
64-Slot DSP with Alogrithms in RAM
Flash 24K x 16
RAM 2K x 16
P16 Processor 256 x 16 RAM 1K x 16 ROM X1, X2, LFT RESET PDWN CKOUT MIDI UART 3 x Timers Standard ATSAM97xx Control Registers
Memory Manager Unit
Ports & Flash Control Registers
P0[15:0] P1[15:0] P2[15:0] P3[15:0]
Clock & PLL
DSP Engine
The DSP engine operates on a frame-timing basis with the frame subdivided into 64 process slots. Each process is itself divided into 16 microinstructions known as "algorithms". Up to 32 DSP algorithms can be stored on-chip in the Alg RAM memory, allowing the device to be programmed for a number of audio signal generation/processing applications. The DSP engine is capable of generating 64 simultaneous voices using algorithms such as wavetable synthesis with interpolation, alternate loop and 24 dB resonant filtering for each voice. Slots may be linked together (ML RAM) to allow implementation of more complex synthesis algorithms. A typical musical instrument application will use a little more than half the capacity of the DSP engine for synthesis, thus providing state-of-the-art 38-voice synthesis polyphony. The remaining processing power may be used for typical functions like reverberation, chorus, surround effect, equalizer, etc. Frequently accessed DSP parameter data are stored in five banks of on-chip RAM memory. Sample data, which is accessed relatively infrequently, can be stored in the built-in Flash 3
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memory, or in external ROM. The combination of localized micro-program memory and localized parameter data allows microinstructions to execute in 31 ns (32 MIPS). Separate buses from each of the on-chip parameter RAM memory banks allow highly parallel data movement to increase the effectiveness of each microinstruction. With this architecture, a single microinstruction can accomplish up to 6 simultaneous operations (add, multiply, load, store, etc.), providing a potential throughput of 192 million operations per second (MOPS).
P16 Control Processor and I/O Functions
The P16 control processor is a general-purpose 16-bit CISC processor core, which runs from external memory. A debug ROM is included on-chip for easy development of firmware directly on the target system. This ROM also contains the necessary code to directly program the built-in Flash memory. The P16 includes 256 words of local RAM data memory for use as registers, scratchpad data and stack. The P16 control processor writes to the parameter RAM blocks within the DSP core in order to control the synthesis process. In a typical application, the P16 control processor parses and interprets incoming commands from the MIDI UART and then controls the DSP by writing into the parameter RAM banks in the DSP core. Slowly changing synthesis functions, such as LFOs, are implemented in the P16 control processor by periodically updating the DSP parameter RAM variables. The P16 control processor interfaces with other peripheral devices, such as the system control and status registers, the on-chip MIDI UART, the on-chip timers and the Ports & Flash control registers through specialized "intelligent" peripheral I/O logic. This I/O logic automates many of the system I/O transfers to minimize the amount of overhead processing required from the P16.
Memory Management Unit (MMU)
The Memory Management Unit (MMU) block allows Flash and/or RAM memory resources to be shared between the synthesis/DSP and the P16 control processor. This allows the single built-in Flash memory to serve as sample memory storage for the DSP and as program storage for the P16 control processor. An internal 2K x 16 RAM is also connected to the MMU, allowing RAM resources to be shared between the DSP and the P16. Similarly, when using external memory, corresponding memory resources can be shared between the DSP and the P16.
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Pin Description
Pins by Function
Table 1. Power Supply
Pin Name GND VC3 VCC Note: Pin Number 5, 10, 18, 22, 33, 45, 47, 59, 62, 75, 88, 99 3, 11, 21, 27, 61 17, 31, 46, 57, 73, 87, 100 Type PWR PWR PWR Function Digital Ground: All pins should be connected to a ground plane Core Power Supply, 3V to 3.8V: All pins should be connected I/O Power Supply, 3V to 5.5V: All pins should be connected to a VCC plane
Power supply decoupling: Like all high speed HCMOS ICs, proper decoupling is mandatory for reliable operation and RFI reduction. The recommended decoupling is 100 nF at each corner of the IC with an additional 10 FT bulk capacitor close to the X1, X2 pins.
Table 2. Single Function Pins
Pin Name CLBD WSBD DABD0 P3.12 - P3.14 X1 Pin Number 26 37 35 81, 23, 24 13 Type OUT OUT OUT Programmable IN Function External DAC serial bit clock External DAC left/right clock External DAC serial stereo audio data General purpose I/O Crystal connection, or external clock input at 256*Fs, Fs being the sampling frequency. When used as an input, a 330 ohms serial resistor should be inserted. Typical crystal frequency is 8 MHz (Fs = 32 kHz) Other end of crystal connection. Cannot be used to drive external circuitry. Buffered X2 output, can be used to drive external circuits, such as Sigma/Delta DACs Built-in PLL compensation filter input Master reset, active low, has built-in Schmitt trigger. Power down, active low Test pins. Should be grounded for normal operation. TEST0 is used to start the built-in debugger. In this case TEST2 specifies the communication baud rate.
X2 CKOUT LFT RESET PDWN TEST[2:0]
14 95 12 15 16 42 - 44
OUT OUT Analog IN IN IN
Note:
Pin names exhibiting an overbar (PDWN for example) indicate that the signal is active low.
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Table 3. Double Function Pins
Name #1 P0.0 - P0.15 P1.0 - P1.15 P2.0 P2.1 P2.2 P2.3 P2.4 Name #2 WA[15:0] WD[15:0] WCS0 WCS1 WOE WWE RBS Pin Number 48, 51, 52, 55, 56, 58, 60, 63 - 65, 67 - 72 83 - 86, 89 - 92, 96 - 98, 1, 2, 6, 8, 9 39 40 41 38 29 Function #1 - General-purpose I/O #2 - External expansion memory address (output) #1 - General-purpose I/O #2 - External expansion memory data (I/O) #1 - General Purpose I/O #2 - Expansion ROM chip select (output, active low) #1 - General-purpose I/O #2 - Expansion RAM chip select (output, active low) #1 - General-purpose I/O #2 - Expansion memory enable (output, active low) #1 - General-purpose I/O #2 - Expansion RAM write enable (output, active low) #1 - General-purpose I/O #2 - Expansion RAM byte select, allows connection of 8-bit external SRAM with 16-bit access in two cycles (output, active low) #1 - General-purpose I/O #2 - Expansion memory address, allows up to 2M x 16 external memory (output) #1 - General-purpose I/O #2 - Host processor chip select (input, active low) #1 - General-purpose I/O #2 - Host processor read (input, active low) #1 - General-purpose I/O #2 - Host processor write (input, active low) #1 - General-purpose I/O #2 - Host processor data (0) - command/status (1) select (input) #1 - General-purpose I/O #2 - Secondary DAC serial stereo audio data (output) #1 - General-purpose I/O #2 - External ADC serial stereo audio data (input) #1 - General-purpose I/O #2 - Host processor data bus (I/O) #1 - General-purpose I/O #2 - Host processor interrupt request, active high, tristate output #1 - General-purpose I/O #2 - High indicates that DSP synthesis is up and running
P2.5 - P2.9
WA[20:16]
74, 78 - 80, 82
P2.10 P2.11 P2.12 P2.13
CS RD WR A0
94 77 76 66
P2.14 P2.15 P3.0 - P3.7 P3.8
DABD1 DAAD0 D[7:0] IRQ
36 34 25, 28, 30, 32, 49, 50, 53, 54 4
P3.9
RUN
20
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Table 3. Double Function Pins (Continued)
Name #1 P3.10 P3.11 P3.15 Name #2 MIDI_IN MIDI_OUT DAAD1 Pin Number 19 7 93 Function #1 - General-purpose I/O #2 - Serial MIDI_IN (input) #1 - General-purpose I/O #2 - Serial MIDI_OUT (output) #1 - General-purpose I/O #2 - Secondary ADC serial stereo audio data (input)
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Table 4. Pinout by Pin Number
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Signal Name P1.11/WD11 P1.12/WD12 VC3 P3.8/IRQ GND P1.13/WD13 P3.11/MIDI_OUT P1.14/WD14 P1.15/WD15 GND VC3 LFT X1 X2 RESET PDWN VCC GND P3.10/MIDI_IN P3.9/RUN VC3 GND P3.13 P3.14 P3.0/D0 Pin # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal Name CLBD VC3 P3.1/D1 P2.4/RBS P3.3/D2 VCC P3.3/D3 GND P2.15/DAAD0 DABD0 P2.14/DABD1 WSBD P2.3/WWE P2.0/WCS0 P2.1/WCS1 P2.2/WOE TEST0 TEST1 TEST2 GND VCC GND P0.0/WA0 P3.4/D4 P3.5/D5 Pin # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal Name P0.1/WA1 P0.2/WA2 P3.6/D6 P3.7/D7 P0.3/WA3 P0.4/WA4 VCC P0.5/WA5 GND P0.6/WA6 VC3 GND P0.7/WA7 P0.8/WA8 P0.9/WA9 P2.13/A0 P0.10/WA10 P0.11/WA11 P0.12/WA12 P0.13/WA13 P0.14/WA14 P0.15/WA15 VCC P2.5/WA16 GND Pin # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal Name P2.12/WR P2.11/RD P2.6/WA17 P2.7/WA18 P2.8/WA19 P3.12 P2.9/WA20 P1.0/WD0 P1.1/WD1 P1.2/WD2 P1.3/WD3 VCC GND P1.4/WD4 P1.5/WD5 P1.6 /WD6 P1.7/WD7 P3.15/DAAD1 P2.10/CS CKOUT P1.8/WD8 P1.9/WD9 P1.10/WD10 GND VCC
Figure 3. Package Description: PQFP100, Pitch = 0.65 mm
80 81 DREAM ATSAM9743
R
51 50
100 1 30
31
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Absolute Maximum Ratings
Table 5. Absolute Maximum Ratings
Ambient Temperature (Power Applied) ............ -40C to + 85C Storage Temperature.......................................-65C to + 150C Voltage on any pin (except X1)....................-0.5V to VCC + 0.5V Voltage on X1 pin.........................................-0.5V to VC3 + 0.5V VCC Supply Voltage.............................................-0.5V to + 6.5V VC3 Supply Voltage.............................................-0.5V t0 + 4.5V Maximum IOL per I/O pin .................................................4.4mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect device reliability.
Recommended Operating Conditions
Table 6. Recommended Operating Conditions
Symbol VCC VC3 tA Parameter Supply voltage (I/O) Supply voltage (Core) Operating ambient temperature Min 3 3 0 Typ 3.3/5.0 3.3 Max 5.5 3.8 70 Unit V V C
DC Characteristics
Table 7. DC Characteristics (TA = 25C, VCC = 5V 10%, VC3 = 3.3V 10%)
Symbol VIL VIH VOL VOH ICC Parameter Low-level input voltage High-level input voltage Low-level output voltage at IOL = -3.2 mA(1) High-level output voltage at IOH = 0.8 mA(2) Power supply current (crystal frequency = 8 MHz) Power down supply current Notes: 1. IOL: Low-level output current. 2. IOH: High-level output current. VCC 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 2.8 4.5 60 TBD TBD 80 TBD 150 Min -0.5 -0.5 2.3 3.3 Typ Max 1.0 1.7 VCC + 0.5 VCC + 0.5 0.45 0.45 Unit V V V V mA A
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Timing Diagrams
External Memory (16 bits)
All timing conditions: VCC = 5V, VC3 = 3.3V, TA = 25C, 30 pF load capacitance on all outputs except X2. All timings refer to tCK, which is the internal master clock period. tCK = tXTAL/4 (typ 31.25 ns). Figure 4. External ROM/RAM (16 bits)
tCSDV
WCS0 WCS1
tRWCSH
tRW
WOE WWE
tRWDV
WD[15:0]
tRWDX
tAVDV
WA[20:0]
tRWHADX
Table 8. Parameters for External Memory Read/Write Cycle (16 bits)
Symbol tCSDV tRWDV tAVDV tRW tRWHCSH tRWHADX tRWDX Parameter Access time from WCSx low Access time from WOE, WWE low Access time from address valid WOE, WWE pulse width WCSx high from rising WOE or WWE Address valid after rising WOE or WWE Data hold time from rising WOE or WWE 10 10 10 6 x tCK Min 5 x tCK - 5 3 x tCK - 5 5 x tCK - 5 4 x tCK Typ Max Unit ns ns ns ns ns ns ns
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External Ram (8 bits)
Figure 5. 8-bit SRAM Read Cycle
tRC
WCS1
tCSOE
WA[20:0]
tPOE
WOE WWE
tORB tACE
RBS
tOE
WD[7:0] Low
tACH
tDF
High
Note:
By setting the SRAM 8-bit in the P16 control word, external RAM can be configured to read 16-bit with 2 x 8-bit accesses.
Figure 6. 8-bit SRAM Write Cycle
t WC
WCS1
tCSWE
WA[20:0]
WOE
t WP
WWE RBS
t WP tAS
tDW1 tDH1
WD[7:0] Low
tDW2
High
tDH2
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Table 9. Parameters for External 8-bit SRAM Read/Write
Symbol tRC tCSOE tPOE tACE tOE tORB tACH tDF tWC tCSWE tWP tDW1 tDH1 tAS tDW2 tDH2 Parameter Word (2 x bytes) read cycle time Chip select low. Address valid to WOE low Output enable pulse width Chip select. Access low byte access time. Output enable low byte access time Output enable low to byte select high Byte select high byte access time Chip select or WOE high to input data HI-Z Write (2 x bytes) write cycle time 1st WWE low from CS or address or WOE Write (low and high byte) pulse width Data out low byte setup time Data out low byte hold time RBS high to second write pulse Data out high byte setup time Data out high byte hold time 2 x tCK- 5 0 5 x tCK 2 x tCK - 10 1.5 x tCK - 5 1.5 x tCK - 10 0.5 x tCK + 10 0.5 x tCK - 5 2 x tCK - 10 10 2 x tCK - 5 6 x tCK 3 x tCK - 5 tCK - 5 tCK Min 5 x tCK 2 x tCK - 5 3 x tCK Typ Max 6 x tCK 3 x tCK + 5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Parallel Interface
Figure 7. Host Interface Read Cycle
A0 tAVCS CS tCSLRDL RD tRDLDV D[15:0] tDRH tPRD tRDHCSH
Figure 8. Host Interface Write Cycle
A0 tAVCS CS tCSLWRL WR tDWS D[15:0] tPWR tWRHCSH
tDWH
Table 10. Parameters for the Parallel Interface
Symbol tAVCS tCSLRDL tRDHCSH tPRD tRDLDV tDRH tCSLRWRL tWRHCSH tPWR tDWS tDWH Parameter Address valid to chip select low Chip select low to RD low RD high to CS high RD pulse width Data out valid from RD Data out hold from RD Chip select low to WR low WR high to CS high WR pulse width Write data setup time Write data hold time 5 5 5 50 10 0 Min 0 5 5 50 20 10 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns
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Digital Audio Timing
Figure 9. Digital Audio Timing Diagram
tCW WSBD tCW tCLBD
CLBD tSOD DABDx DAADx tSOD
Figure 10. Digital Audio Frame Format
WSBD (I2S) WSBD (Japanese) CLBD
DABDx DAADx MSB LSB (16 bits)
0000000000000 MSB LSB (20 bits) LSB (18 bits)
Table 11. Digital Audio Timing Parameters
Symbol tCW tSOD tCLBD Parameter CLBD rising to WSBD change DABDx/DAADx valid prior/after CLBD rising CLBD cycle time Min 8 x tCK - 10 8 x tCK - 10 16 x tCK Typ Max Unit ns ns ns
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Overview of Operation
Normal Operation Mode
This section limits its contents to a description of the operation and registers specific to the ATSAM9743. A familiar understanding of the ATSAM97xx series operation is required. TEST2 = TEST1 = TEST0 = O: In this mode, the built-in Flash is assumed to be already programmed. After RESET, all pins are in configuration #1 and all general purpose I/Os (64 pins) are in input mode with a weak pull-down resistor. The P16 program starts at address 8000H, which is the first word of the internal Flash. The program coded in Flash or into external memory has access to nine specific 16-bit registers as follows. I/O Configuration Register Address 20:0808H (Read/Write)
D15 X D14 X D13 MIDI_ OUT D12 MIDI_ IN D11 RUN D10 D9 D8 IRQ D7 HOST D6 AD20 D5 AD19 D4 AD18 D3 AD17 D2 AD16 D1 ROM D0 RAM
DAAD0 DABD1
This register is cleared at reset. A one written to the register indicates that the corresponding alternate configuration #2 is selected as follows: * * * * * * RAM: WA[15:0], WD[7:0], WCS1, WOE, WWE, RBS ROM: WCS0, WD[15:8] AD[20:16], Respective WA[20:16] signals HOST: CS, RD, WR, A0, D[7:0] IRQ: IRQ DABD1, DABD0, RUN, MIDI_IN, MIDI_OUT: Corresponding pins These four registers (one for each General-purpose I/O port P0 to P3) are cleared at reset, thus putting all port bits in input mode. A one in a given bit position configures the corresponding port bit in output mode (assuming that no alternate function is selected for the port bit). These four registers (one for each General Purpose I/O port P0 to P3) are cleared at powerup. A 0/1 written in a given bit position sets the corresponding port bit to 0/1, assuming that no alternate function is selected for the port bit and that the port bit is in output mode. A read from the register always returns the value written to the register independently of the actual port configuration. I/O Data Reads Registers Address 20:810H to 20:0813H (Read-only) A read from these registers always returns the value of the pins independently of the configuration. For example, suppose that P3.10 is configured as MIDI_IN, then setting the direction to output and writing data to P3.10 will have no effect. However, the actual value of the MIDI_IN pin would be read.
I/O Direction Registers Address 20:0804H to 20:0807H (Read/Write)
I/O Data Write Registers Address 20:0800H to 20:803H (Read/Write)
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On Board Flash Program/Debug Mode
TEST1 = 0, TEST0 = 1: In this mode, the P16 program starts in the built-in debug ROM. All ports are set to input mode with a weak pull-down, except P3.10 and P3.11 which are set to MIDI_IN and MIDI_OUT, respectively. If TEST2 = 0, the baud rate is set to the MIDI standard (31250 baud). If TEST2 = 1 the baud rate is set to 57600 baud. This later setting is useful when Flash programming time is a production cost issue. Programming the built-in Flash, or debugging a P16 program, occurs exclusively through the MIDI_IN and MIDI_OUT pins, which means that any firmware can be debugged except the MIDI part of the firmware (note that as the ATSAM9743 is compatible with the ATSAM97xx series, it is easy to debug the MIDI with another development board such as 97PNP2).
MIDI_IN Commands
The following is only given for information purposes, as the CV9743 CodeView debugger takes care of all the protocol handling between a PC and the ATSAM9743 target board. Commands are received through MIDI_IN, all commands except GO and GR are acknowledged. A new command should not be sent until the acknowledge from a previous command is received. Note that the commands are compatible with the standard Debug program from the ATSAM97xx series. The first command sent to the ATSAM9743 after reset should be INIT (0F0H).
Table 12. Parameters for MIDI_IN/MIDI_OUT Commands and Answers
MIDI_IN Command INIT 0F0H RDIRAM 00H WRIRAM 01H RDXTMEM 02H WRXTMEM 03H RDIO 04H WRIO 05H RDSAML 06H RDSAMH 07H WRSAM 08H Byte Parameters - ad ad, dl, dh adl, adh, pl, ph adl, adh, pl, ph, dl, dh ioad ioad, dl, dh samadl, samadh samadl, samadh samadl, samadh, d0, d1, d2, d3 adl, adh Dummy adl, adh, pl, ph, sizel, sizeh MIDI_OUT Answer Ack (0ACH) dl, dh Ack (0ACH) dl, dh Ack (0ACH) Description Establish link. This should be the first command sent after reset. Read P16 IRAM at ad Write dh/dl at P16 IRAM address ad Read word of P16 external memory at address ph/pl:adh/adl. Note that from a P16 point of view, the built-in Flash and 2K x 16 SRAM are external memory. Write dh/dl word of data to P16 external memory at address ph/pl:adh/adl. If the address falls into the Flash range, then Flash-programming algorithm is applied. Ack is returned after the write is completed. Read P16 I/O at ioad Write dh/dl at I/O address ioad Read low word of synthesis DSP RAM at samadh/samadl Read high word of synthesis DSP RAM at samadh/samadl Write 32 bits (d3/d2/d1/d0) of data to Synthesis DSP RAM at address samadh/samadl Jump to adh/adl (start firmware) Restore firmware context Read size words of external memory starting at address ph/pl/adh/adl
dl, dh Ack (0ACH) dl, dh dl, dh Ack (0ACH)
GO 09H GR 0AH RDBLOCK 0BH
See note See note 2*size bytes
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Table 12. Parameters for MIDI_IN/MIDI_OUT Commands and Answers (Continued)
WRBLOCK 0CH adl, adh, pl, ph, sizel, sizeh, 2*size data bytes adl, adh, size, 2*size bytes Ack (0ACH) Write size words to external memory starting at address ph/pl:adh/adl. This will NOT work if the address is in the Flash range. Use WRFLASH command for block programming of the built-in Flash. Write size words (max 32) to Flash, starting at address 8000H + adh/adl. The block written shall not cross a 32 words Flash page. Before actually writing to the Flash, Ack is returned immediately after the last data byte is received, thereby allowing masked time Flash programming. Ack is returned when the current Flash write has been completed, thus allowing monitoring of the completion of the last WRFLASH.
WRFLASH 0DH
Ack (0ACH)
CHKFLASH 0EH
Dummy
Ack (0ACH)
Breakpoint Settings
Breakpoint is set by replacing a firmware instruction by the single word ROM Debug instruction. This instruction jumps into the ROM debug code, saves the caller program context and sends data AAH, 55H to MIDI_OUT. This signals the 9743CV program that a breakpoint has been reached. Further program execution will be done by restoring the instruction at the breakpoint address, modifying the context stack (IP = IP-1) and issuing a GR command. The GR command restores the user program context and resumes execution at the restored instruction. The debugger needs the following resources to operate: * * * One word at address 18H in IRAM 18 words of stack 8 words starting at address 20:0000H in built-in SRAM for FIFO
Debugger Requirements
An additional 32 words of SRAM (20:0008H to 20:0027H) are needed for block Flash programming (WRFLASH). Specific Flash functions such as chip erase, signature fuse, etc. can be externally triggered by using combinations of the above commands.
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Flash Program and Test Registers
FADDTEST Register Address 0020:080AH (Read/Write) FDI Register Address 0020:080BH (Read/Write) FCOMMAND Register Address 0020:0809H (Cleared at RESET time) (Read/Write)
D15 D14 D13
Three additional write I/O registers and two read I/O registers are implemented for the built-in Flash program and test, as follows.
This 15-bit register provides the addtest<14:0> address bus to the Flash block. This is the address register when programming the Flash.
This 16-bit register provides the di<15:0> data bus to the Flash block. This is the data register when programming the Flash.
D12
D11
D10 RSTT
D9 CEN
D8 WE
D7
D6
D5 TM5
D4 TM4
D3 TM3
D2 TM2
D1 TM1
D0 TM0
PAGEM PAGE1
*
RSTT,CEN, WE, PAGEM, PAGE1,TM5-TM0: Signals sent to corresponding Flash block inputs. These signals, with proper timing, provide Flash programming.
FSTATUS Register Address 0020:0809H (Read-only)
D15 X D14 X D13 X D12 X D11 X D10 D9 D8 D7 X D6 X D5 X D4 X D3 X D2 X D1 D0
TEST2 TEST1 TEST0
DOUTEN RDYBSYN
* *
RDYBSYN and DOUTEN: These Flash signals provide write-progress monitoring respectively. TEST0-TEST2: Input pins, respectively. Reads the dotest <15:0> Flash data output bus for test modes.
FDOTEST Register (Read-only)
18
ATSAM9743
1773B-DRMSD-11/02
ATSAM9743
Memory Map
Table 13. Description of the ATSAM9743 Memory Map
Address Low 0000:0000 0000:0100 0000:400 0000:8000 0000:E000 0020:0000 0020:0800 0020:0816 0200:0000 Note: Address High 0000:00FF 0000:03FF 0000:7FFF 0000:DFFF 001F:FFFF 0020:07FF 0020:0815 01FF:FFFF 021F:FFFF Access ATSAM97xx Standard Routine ROM Built-in ROM for Flash program & debug routines Optional external ROM Built-in Flash (24K x 16) Optional external ROM (WCS0) Built-in SRAM (2K x 16) ATSAM9743 specific I/Os Not used Optional external RAM (WCS1)
If programmed as an alternate function, WCSO is generated even if the firmware accesses the built-in Flash or ROM. In this case the external ROM data is not used.
Flash Programing Performance
Crystal Compensation/ LFT FIlter
Typical programming times for the 24K x 16 Flash are as follows: MIDI baud rate 31250 bauds, TEST0 = 1, TEST2 = 0: 33 seconds 57600 bauds, TEST0 = 1, TEST2 = 1: 19 seconds Figure 11. Recommended Crystal Compensation and LFT Filter
X1 X1 X2 LFT C2 22p C3 10n R1 100
Note:
The ATSAM9743 uses a low power oscillator. No compensation capacitor is necessary. However, because the crystal drive is very small, it is mandatory to keep the X1/X2 traces as small as possible.
19
1773B-DRMSD-11/02
Mechanical Dimensions
Figure 12. ATSAM9743 Mechanical Dimensions
Table 14. ATSAM9743 Plastic Lead Quad Flat Pack (PQFP100)
Min A A1 A2 D D1 E E1 L P B 0.22 0.65 0.25 2.55 2.8 17.9 14.0 23.9 20 0.88 0.65 0.38 1.03 3.05 Nom Max 3.4
20
ATSAM9743
1773B-DRMSD-11/02
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1773B-DRMSD-11/02 0M

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